This invention relates generally to central processing units (CPUs) as used in data processing systems and is particularly directed to an arrangement for controlling the operating speed of a CPU.
Many data processing systems include a microcomputer, microprocessor, or central processor unit (CPU), as these terms are used interchangeably in the present application. The control portion of a CPU either contains a clock circuit or has provisions for an external clock input. The clock circuit delivers regular timed signals that serve as the timekeeping mechanism for the CPU. Each event in a sequence occurs in synchronization with the next "clock time" or in response to a signal controlled by the clock and various forms of logic. CPUs typically take several clock periods to accomplish a fetch and several more for execution, so that an instruction cycle may contain on the order of 10 to 20 clock cycles. Most CPUs use crystal controlled clocks. While specific operating frequencies can vary, the stability of these frequencies cannot. In addition, any timing done in software requires the frequency stability of a crystal controlled oscillator.
The rate at which the CPU performs various operations one after another or in the form of a succession of steps controlled by a program is defined by the operating frequency of its clock circuit or crystal oscillator. The higher the operating frequency of the crystal oscillator, the faster the CPU is able to a accomplish various tasks and the greater the throughput in the data processing system. However, the operation of a CPU at a single speed, whether characterized by a high frequency or a low frequency, limits its interfacing flexibility in terms of hardware with which it is compatible and software which controls its operation.
The present invention provides a dual operating speed capability for a CPU which enhances the CPU's interfacing flexibility and permits the CPU to operate at higher speeds for increased data throughput.